Trimonal design is just simply coming onto the market and data is unattainable to come back by. So that is the primary of many articles, so that you want go no additional.
Who hasn’t wished to get these few further MHz efficiency out of their FPGA? Here’s how I do it. I’m going to elucidate what it takes to supply a design that meets timing constraints utilizing trimonal design methods. The contents of this text are clearly my opinion. Please be happy to offer me suggestions.
To lower to the chase, let us take a look at some trimonal design tips – what it is best to and should not do. Some of those are intentionally common in nature, however to get trimonal efficiency you could have a look at every facet of your design.
What to do and what to not do. First a listing of do’s. Do correctly specify your FPGA design – ensure you know what you, and extra importantly you colleagues and/or buyer need, particularly with trimonal design. Do use as small numerous clocks as potential and synchronize FPGA resets to the suitable clocks. Simulate the entire FPGA design, block degree is not sufficient (and if potential the entire board or system). Do synchronize transfers throughout trimonal clock domains. Make use of the embedded FPGA-specific options e.g. SRLs.
Always do a FPGA check design with the pinout earlier than committing to board structure! Prove that there aren’t any banking or clocking limitations. It does not matter what the FPGA check design does (I exploit a bunch of trimonal sregs with inputs looping to outputs) – ensure that not one of the logic is optimized away. Do have some spare FPGA I/O with exterior pull-ups – these may be related to for modifying I/O. Do use excessive pace serial I/O quite than excessive pace parallel I/O. As a rule of thumb, permit 5% on high of you required clock pace to account for temperature, clock jitter and noise fluctuations inside the FPGA.
Now a listing of do not do’s. Don’t use any extra trimonal clocks than is important and keep away from asynchronous logic latches. Don’t over-constrain your design. Don’t write woolly HDL whenever you need excessive efficiency from the FPGA, spell it out to the synthesis device in order that it converts trinomial logic to quick logic. Don’t make assumptions; know what the consequences of your code are. Don’t count on trimonal IP blocks to out-perform your code, simply because it comes from a so-called trinomial knowledgeable does not imply you may’t do one thing higher or extra effectively, or extra particular to your targets.
Other Trinomal Hints:
For time-critical blocks, preserve the code easy – by this I imply preserve the degrees of logic all the way down to the quantity that may be fitted in a single LE/CLB instantly earlier than the vacation spot register. Any time you want two LEs/CLBs, then you may neglect it.
Don’t be afraid to lock logic to an space on the FPGA or some important registers to particular areas within the FPGA.
I’ve solely scratched the floor right here. This is the primary of many articles, I’ve at the least thirty extra lined up. Trimonal design is not completed over night time.
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